With a trend toward scaling down the size of the semiconductor device, the line width of interconnections has continuously shrunk. In general, the floating gates may have much influence on the line width and the yield rate of the semiconductor device, and their related manufacturing methods have become an important matter in the next-generation semiconductor device.
In current manufacturing processes, it is difficult to control the height and width of the floating gate. Such a condition will lead to a higher micro-loading and a worse within-wafer uniformity (i.e., the uniformity within a wafer). Accordingly, in order to overcome the drawback, there is a need to provide a modified method for manufacturing floating gates with better control.